The 6502 chip design used precharging for exactly that reason. You precharge to Vdd in phase 1 through a path with high drive strength and then in phase 2 only the fast pull-down network has to do any work if needed. The pull-up network is still there to prevent floating and hence needs to be ratioed against the pull-down on-resistance to pass a strong 0, but the pull-up resistance no longer sets the low-to-high switching time. The main limitation is that it can only handle monotonic logic, so you may need to interpose static inverting logic stages between your precharge logic stages.
And in standard chips nowadays, you can still find transmission gate logic (complementary pass transistors so you can pass both strong 1s and strong 0s), pseudo-NMOS logic (using a boring old enhancement mode PMOS transistor tied off to ground as a pull-up resistor) and domino logic (precharge logic with interleaved CMOS stages) in critical datapath circuits, so even in a bog standard CMOS process there's room for trickery.
> The drawback is that it's harder to manufacture a chip with both N-channel and P-channel transistors.
Yeah, and CMOS wasn't competitive for higher speed chips until the 80s (the 68000 was NMOS based until 1985 and some higher end processors eschewed MOS and used bipolar ECL). CMOS had been around for a good while at that point but was mainly used for applications like battery-powered watches and calculators where static power draw was more important than speed. The 65C02 (a CMOS version of the 6502 with a few other features thrown in) came out in 78 and was competitive in speed to the original 6502, though it was originally designed for a customer for use in calculators, but of course ended up being used in numerous home computers.
And in standard chips nowadays, you can still find transmission gate logic (complementary pass transistors so you can pass both strong 1s and strong 0s), pseudo-NMOS logic (using a boring old enhancement mode PMOS transistor tied off to ground as a pull-up resistor) and domino logic (precharge logic with interleaved CMOS stages) in critical datapath circuits, so even in a bog standard CMOS process there's room for trickery.
> The drawback is that it's harder to manufacture a chip with both N-channel and P-channel transistors.
Yeah, and CMOS wasn't competitive for higher speed chips until the 80s (the 68000 was NMOS based until 1985 and some higher end processors eschewed MOS and used bipolar ECL). CMOS had been around for a good while at that point but was mainly used for applications like battery-powered watches and calculators where static power draw was more important than speed. The 65C02 (a CMOS version of the 6502 with a few other features thrown in) came out in 78 and was competitive in speed to the original 6502, though it was originally designed for a customer for use in calculators, but of course ended up being used in numerous home computers.